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Understanding DDR Memory
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Short for "Double Data Rate", DDR technology doubles the bandwidth of SDRAM under optimal conditions. This is to say that twice as much data can be transferred between the memory and system during the same amount of time. This is because DDR SDRAM sends and receives data twice as often as common SDRAM.
Remember that SDRAM transfers data on every clock cycle (to be specific, on the rising edge of every clock cycle). DDR, on the other hand, transfers data on both the rising edge (clock signal bounces from LOW to HIGH) and the falling edge (clock signal bounces from HIGH to LOW) of a clock cycle. Therefore, two bits (per data line) are transferred every clock cycle. In order to do this, two bits are accessed from the memory array (where data is actually stored) for each data line on every clock cycle, this process is called the "2-bit prefetch".
A DDR200 module provides a data bandwidth of 1.6GB/s - we also call this PC1600 memory. Likewise, DDR400 is also called PC3200 memory, because it provides 3.2GB/s bandwidth. You can double the bandwidth by using same-speed memory modules in dual channel mode if your system supports it: dual channel DDR400 is capable of delivering 6.4GB/s bandwidth.
As 2nd generation DDR, the most important improvement found in DDR2 memory is its transfer data rate or bandwidth. As in the case with DDR SDRAM vs. SDRAM, the bandwidth of DDR2 memory can double that of DDR.
The DDR standard stops at DDR400 (of course, there are lots of DDR500 and even DDR600 products on market, but these are for overclockers), which provides 3.2GB/s bandwidth (single channel). The DDR2 standard starts from DDR2 400 and goes all the way up to DDR2 800 or even higher. DDR2 800 or PC2 6400 can provide 6.4GB/s bandwidth (single channel), twice as much as DDR400. Dual channel DDR2 800 will offer an unparalleled 12.8GB/s bandwidth, which is a huge leap from the 6.4GB/s bandwidth of dual channel DDR400 memory.
Since DDR already transfers data on both the rising and falling edges of a clock cycle, how does DDR2 double the bandwidth yet again? The answer lies in the I/O buffer frequency, which is doubled with DDR2. The memory controller in our systems only deal with the I/O buffer on the memory chip. To double the data from the memory array to the I/O buffer, DDR2 utilizes a "4-bit prefetch" as opposed to the "2-bit prefetch" with DDR. This means that 4 bits of data are moved from the memory array to the I/O buffer per data line each core clock cycle.
The core clock cycle here refers to the cycle time of the memory array, and the frequency of the memory array is half that of the I/O buffer and 1/4 of the data rates. Take DDR2 800 for example: it has an 800MHz data rate, the I/O buffer works at 400MHz, and the core frequency of the memory array is only 200MHz. The core frequency remains the same as DDR400. However, the DDR400 I/O buffer operates at 200MHz. The time of "a core cycle" is therefore the same whether it is DDR400 or DDR2 800.
DDR2 chips may look different than DDR as well, because most DDR chips use the TSOP-II (Thin Small-Outline Package) form factor while DDR2 utilizes the FBGA (Fine Ball Grid Array) form factor, which is smaller in size than TSOP-II. FBGA chips also feature less electrical noise than TSOP-II, thus resulting in improved signal integrity at high operating frequencies. Besides the enhanced bandwidth, DDR2 also uses less power than DDR by operating on 1.8V - a 28% reduction compared to DDR (2.5V). DDR2 has power saving features such as smaller page sizes and an active power down mode too. These power consumption advantages make DDR2 memory especially suitable for use in notebook computers.
Supplemental Information: ODT, OCD and Other Memory Technology
DDR-supporting motherboard typically have several resistors around the memory slots that are called termination resistors, which are used to eliminate excessive signal noise. These resistors are missing on motherboards utilizing DDR2 memory modules, since the termination resistors are built into each of the memory chips on the module, which is far closer to the source of the noise. This feature is called ODT or On-Die Termination, and it can reduce interference within the chip, thus guaranteeing the stability and reliability of DDR2 memory when working under high frequencies.There are other features such as Posted CAS and Additive Latency, which work together to prevent data collisions and utilize the data bus more efficiently; and the Off-Chip Driver calibration (OCD), which increases signal integrity and system timing margin as well.
Third generation DDR memory leaps greatly forward in data transfer rate and power management. DDR3 provides even higher bandwidth than DDR2 due to the 8-bit prefetch buffer (4-bit prefetch of DDR2, and 2-bit of DDR). The advanced fabrication technology allows lower operating currents and voltages (1.5V, compared to 1.8V of DDR2) and thus enhances thermal performance. Cooler operating temperatures make DDR3 the best choice for mobile operations. DDR3 memory modules take the form of 240-pin DIMMs, and are not compatible with DDR2 memory slots.