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Intel I350-T4V2 4-Port PCI-E X4 Gigabit Ethernet Network Card 4 RJ45 Ports 10/100/1000Mbps Wired Internal NIC for Server Desktop
- Host lnterface: PCl Express·2.1 5GT/slanex4 lane
- Supports10/100/1000Mbps data rate auto negotiation
- Each port can send and receive eight queue
- Up to 86 pieces of queue receiver to adjust(RSS) in multiple processor system can minimize the use of the CPU
- Support 8 pool of each ports(a single queue) virtual machine device queue(VMDq)
- Support the SR- IOVfunction
- Support direct cache access(DCA)
- Support the lntel l/0V3.0 acceleration technology
- TS0 interleaved technique isto reduce the delay
- To minimize the equipment l/0 interrupt using MSl and MSl -X
- The UDP and TCP and lP checksum partial load
- The UDP and TCP send piecewise load(TS0)
- SCTP receiving and sending oheckand partial load
- The packet combination of interrupt and timer(packet timer) and absolute- interruption
- delay timer is to send and receive operation
- Support PCl Express base specification 2.0(5GTs)
- lntel l350 double integrated MAC+ PHY and SERDES chip oontroller with high
- performance, high reliability and low power consumption characteristics
- Super depth, based on the packet buffer perchannel can reduce the use ofthe CPU
- Hardware acceleration can be partial load taskfrom the main processor The controller can be used for partial load TCP/UDP/lP
- checksum TCP segment
- Server level of reliability, availability and performance characteristics:
- Link aggregation and load balancing
- Relevant switches: 802.3AD(LACP), common Trunking(GEC/FEC)
- Exchange and NIC norelated
- Application
- De
Any questions? Ask CelesteSM will help you find out quickly.
Host lnterface: PCl Express·2.1 5GT/slanex4 lane
Supports10/100/1000Mbps data rate auto negotiation
Each port can send and receive eight queue
Up to 86 pieces of queue receiver to adjust(RSS) in multiple processor system can minimize the use of the CPU
Support 8 pool of each ports(a single queue) virtual machine device queue(VMDq)
Support the SR- IOVfunction
Support direct cache access(DCA)
Support the lntel l/0V3.0 acceleration technology
TS0 interleaved technique isto reduce the delay
To minimize the equipment l/0 interrupt using MSl and MSl -X
The UDP and TCP and lP checksum partial load
The UDP and TCP send piecewise load(TS0)
SCTP receiving and sending oheckand partial load
The packet combination of interrupt and timer(packet timer) and absolute- interruption
delay timer is to send and receive operation
Support PCl Express base specification 2.0(5GTs)
lntel l350 double integrated MAC+ PHY and SERDES chip oontroller with high
performance, high reliability and low power consumption characteristics
Super depth, based on the packet buffer perchannel can reduce the use ofthe CPU
Hardware acceleration can be partial load taskfrom the main processor The controller can be used for partial load TCP/UDP/lP
checksum TCP segment
Server level of reliability, availability and performance characteristics:
Link aggregation and load balancing
Relevant switches: 802.3AD(LACP), common Trunking(GEC/FEC)
Exchange and NIC norelated
Application
De
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- Return for refund within: 30 days
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