Hynix (2 X 256MB) PC-2100R Reg Ecc DDR-266 Memory HYMD232G726B8M-H

Hynix HYMD232G726B(L)8M-M/K/H/L series is Low Profile registered 184-pin double data rate Synchronous DRAMDual In-Line Memory Modules (DIMMs) which are organized as 32Mx72 high-speed memory arrays.
Hynix HYMD232G726B(L)8M-M/K/H/L series consists of nine 32Mx8 DDR SDRAM in 400mil TSOP II packages on a 184pinglass-epoxy substrate.
Hynix HYMD232G726B(L)8M-M/K/H/L series provide a high performance 8-byte interface in5.25" width form factor of industry standard.
It is suitable for easy interchange and addition.

Hynix HYMD232G726B(L)8M-M/K/H/L series is designed for high speed of up to 133MHz and offers fully synchronousoperations referenced to both rising and falling edges of differential clock inputs.
While all addresses and control inputs are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it.
The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth.

All input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable latencies andburst lengths allow variety of device operation in high performance memory system.

Hynix HYMD232G726B(L)8M-M/K/H/L series incorporates SPD(serial presence detect).
Serial presence detect func-tion is implemented via a serial 2,048-bit EEPROM.
The first 128 bytes of serial PD data are programmed by SK Hynix toidentify DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.

Features

• 256MB (32M x 72) Low Profile Registered DDR DIMM based on 32Mx8 DDR SDRAM
• JEDEC Standard 184-pin dual in-line memory module (DIMM)
• Error Check Correction (ECC) Capability
• Registered inputs with one-clock delay
• Phase-lock loop (PLL) clock driver to reduce loading
• 2.5V +/- 0.2V VDD and VDDQ Power supply
• All inputs and outputs are compatible with SSTL_2 interface
• Fully differential clock operations (CK & /CK) with 100MHz/125MHz/133MHz
• Programmable CAS Latency 2 / 2.5 supported
• Programmable Burst Length 2 / 4 / 8 with both sequential and interleave mode
• tRAS Lock-out function supported
• Internal four bank operations with single pulsed RAS
• Auto refresh and self refresh supported
• 8192 refresh cycles / 64ms